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MC14051B, MC14052B, MC14053B Analog Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally-controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved.
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16 PDIP-16 P SUFFIX CASE 648 MC140XXBCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 TSSOP-16 DT SUFFIX CASE 948F 1 VDD Vin, Vout DC Supply Voltage (Referenced to VEE, VSS VEE) Input or Output Voltage Range (DC or Transient) (Referen- ced to VSS for Control Inputs and VEE for Switch I/O) Input Current (DC or Transient) per Control Pin Switch Through Current Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) - 0.5 to +18.0 - 0.5 to VDD + 0.5 V 16 V SOEIAJ-16 F SUFFIX CASE 966 1 mA mA mW C C C XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week MC140XXB AWLYWW 14 0XXB ALYW 140XXB AWLYWW
* * * * * * * * *
Triple Diode Protection on Control Inputs Switch Function is Break Before Make Supply Voltage Range = 3.0 Vdc to 18 Vdc Analog Voltage Range (VDD - VEE) = 3.0 to 18 V Note: VEE must be VSS Linearized Transfer Characteristics Low-noise - 12 nV/Cycle, f 1.0 kHz Typical Pin-for-Pin Replacement for CD4051, CD4052, and CD4053 For 4PDT Switch, See MC14551B For Lower RON, Use the HC4051, HC4052, or HC4053 High-Speed CMOS Devices
v
MAXIMUM RATINGS (Note 1.)
Symbol Parameter Value Unit
Iin ISW PD TA Tstg TL
10 25 500 - 55 to +125 - 65 to +150 260
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE or VDD). Unused outputs must be left open.
v
v
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14051B/D
MC14051B, MC14052B, MC14053B
MC14051B 8-Channel Analog Multiplexer/Demultiplexer
6 11 10 9 13 14 15 12 1 5 2 4 INHIBIT A B C X0 X1 X 3 X2 COMMON X3 OUT/IN X4 X5 X6 X7 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
MC14052B Dual 4-Channel Analog Multiplexer/Demultiplexer
6 10 9 12 14 15 11 1 5 2 4 INHIBIT A X B X0 X1 X2 X3 Y0 Y Y1 Y2 Y3
MC14053B Triple 2-Channel Analog Multiplexer/Demultiplexer
6 11 10 9 12 13 2 1 5 3 INHIBIT X A B C X0 Y X1 Y0 Y1 Z Z0 Z1 14
CONTROLS
CONTROLS
13 COMMONS OUT/IN 3
CONTROLS
15
COMMONS OUT/IN
SWITCHES IN/OUT
SWITCHES IN/OUT
SWITCHES IN/OUT
4
VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be VSS.
PIN ASSIGMENT MC14051B
X4 X6 X X7 X5 INH VEE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD X2 X1 X0 X3 A B C Y0 Y2 Y Y3 Y1 INH VEE VSS
MC14052B
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD X2 X1 X X0 X3 A B Y1 Y0 Z1 Z Z0 INH VEE VSS
MC14053B
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Y X X1 X0 A B C
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3. Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. 4. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to VEE) SUPPLY REQUIREMENTS (Voltages Referenced to VEE) CONTROL INPUTS -- INHIBIT, A, B, C (Voltages Referenced to VSS)
ELECTRICAL CHARACTERISTICS
Capacitance, Feedthrough (Channel Off)
Capacitance, Common O/I
Capacitance, Switch I/O
Off-Channel Leakage Current (Figure 10)
ON Resistance Between Any Two Channels in the Same Package
ON Resistance
Output Offset Voltage
Recommended Static or Dynamic Voltage Across the Switch (4.) (Figure 5)
Recommended Peak-to-Peak Voltage Into or Out of the Switch
Input Capacitance
Input Leakage Current
High-Level Input Voltage
Low-Level Input Voltage
Total Supply Current (Dynamic Plus Quiescent, Per Package
Quiescent Current Per Package
Power Supply Voltage Range
Characteristic
Symbol
Vswitch
ID(AV)
Ron
VOO
VDD
CI/O
CO/I
CI/O
VI/O
Ron
VIH
IDD
Cin
VIL
Ioff
Iin
VDD
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
15
-- --
--
--
--
--
--
--
--
MC14051B, MC14052B, MC14053B
VDD - 3.0 VSS VEE
Control Inputs: Vin = VSS or VDD, VI/O Switch I/O: VEE VDD, and Vswitch 500 mV (4.)
Ron = per spec, Ioff = per spec
Ron = per spec, Ioff = per spec
Pins Not Adjacent Pins Adjacent
Inhibit = VDD (MC14051B) (MC14052B) (MC14053B)
Inhibit = VDD
Vin = VIL or VIH (Control) Channel to Channel or Any One Channel
Vswitch 500 mV Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch)
Vin = 0 V, No Load
Channel On
Channel On or Off
Vin = 0 or VDD
TA = 25_C only (The channel component, (Vin - Vout)/Ron, is not included.)
v v
Test Conditions
v
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v
(4.)
3 MinIII Max Min 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 - 55_C Typical 100 0.1 VDD 800 400 220 600 1.5 3.0 4.0 5.0 10 20 70 50 45 18 -- -- -- -- -- -- -- -- -- -- -- 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 (0.07 A/kHz) f + IDD (0.20 A/kHz) f + IDD (0.36 A/kHz) f + IDD 0.00001 Typ (3.) 0.05 0.005 0.010 0.015 0.15 0.47 2.75 5.50 8.25 2.25 4.50 6.75 250 120 80 5.0 60 32 17 10 25 10 10 10 -- -- -- 25_C 100 1050 500 280 0.1 Max VDD 600 7.5 1.5 3.0 4.0 5.0 10 20 70 50 45 18 -- -- -- -- -- -- -- -- -- -- Min 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 125_C 1000 1200 520 300 Max VDD 135 95 65 300 150 300 600 1.0 1.5 3.0 4.0 18 -- -- -- -- -- -- -- -- -- -- -- Unit VPP mV V A A A nA pF pF pF pF V V V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III I I I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III I I I I II IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III I I I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not lo be used for design purposes but In intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS (5.) (CL = 50 pF, TA = 25_C) (VEE
Crosstalk, Control Input to Common O/I (Figure 9) (R1 = 1 k, RL = 10 k Control tTLH = tTHL = 20 ns, Inhibit = VSS)
Channel Separation (Figure 8) (RL = 1 k, Vin = 1/2 (VDD-VEE) p-p, fin = 3.0 MHz
Off Channel Feedthrough Attenuation (Figure 7) RL = 1K, Vin = 1/2 (VDD - VEE) p-p fin = 4.5 MHz -- MC14051B fin = 30 MHz -- MC14052B fin = 55 MHz -- MC14053B
Bandwidth (Figure 7) (RL = 1 k, Vin = 1/2 (VDD-VEE) p-p, CL = 50pF 20 Log (Vout/Vin) = - 3 dB)
Second Harmonic Distortion (RL = 10K, f = 1 kHz) Vin = 5 VPP
Propagation Delay Times (Figure 6) Switch Input to Switch Output (RL = 10 k) MC14051 tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns
Inhibit to Output (RL = 10 k, VEE = VSS) Output "1" or "0" to High Impedance, or High Impedance to "1" or "0" Level MC14051B
Control Input to Output (RL = 10 k, VEE = VSS) MC14051B
MC14053B
MC14052B
MC14053B
MC14052B
MC14053 tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns
MC14052 tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns
Characteristic
MC14051B, MC14052B, MC14053B
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tPHZ, tPLZ, tPZH, tPZL tPLH, tPHL tPLH, tPHL Symbol BW -- -- -- --
4
v VSS unless otherwise indicated)
VDD - VEE Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
10 10 10 10 10
Typ (6.) All Types
- 50
- 50
0.07
300 120 80
325 130 90
360 160 120
275 140 110
300 155 125
350 170 140
25 8.0 6.0
75 17 30 12 10 35 15 12
Max
600 240 160
650 260 180
720 320 240
550 280 220
600 310 250
700 340 280
65 20 15
75 30 25
90 40 30
-- -- -- -- --
MHz
Unit
mV dB dB ns ns ns ns ns ns ns ns ns %
MC14051B, MC14052B, MC14053B
VDD IN/OUT
VDD
VDD OUT/IN
VEE
VDD LEVEL CONVERTED CONTROL
IN/OUT
OUT/IN
VEE
CONTROL
Figure 1. Switch Circuit Schematic
TRUTH TABLE
Control Inputs Select Inhibit 0 0 0 0 0 0 0 0 1 C* 0 0 0 0 1 1 1 1 x B 0 0 1 1 0 0 1 1 x A 0 1 0 1 0 1 0 1 x MC14051B X0 X1 X2 X3 X4 X5 X6 X7 None None ON Switches MC14052B Y0 Y1 Y2 Y3 X0 X1 X2 X3 MC14053B Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 None X0 X1 X0 X1 X0 X1 X0 X1 INH A B C 6 11 10 9 8 X0 13 X1 14 X2 15 X3 12 X4 1 X5 5 X6 2 X7 4
16
VDD BINARY TO 1-OF-8 DECODER WITH INHIBIT VEE
LEVEL CONVERTER
VSS
7
3X
*Not applicable for MC14052 x = Don't Care
Figure 2. MC14051B Functional Diagram
16 INH 6 A 10 B9 8 X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 VSS 7 LEVEL CONVERTER
VDD 16 BINARY TO 1-OF-4 DECODER WITH INHIBIT VEE
13 X
VDD BINARY TO 1-OF-2 DECODER WITH INHIBIT VEE
14 X
INH A B C
6 11 10 9 8
LEVEL CONVERTER VSS 7
X0 12 X1 13 Y0 2
3Y
Y1 1 Z0 5 Z1 3
15 Y
4Z
Figure 3. MC14052B Functional Diagram
Figure 4. MC14053B Functional Diagram
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MC14051B, MC14052B, MC14053B
TEST CIRCUITS
ON SWITCH CONTROL SECTION OF IC V SOURCE VDD VEE VEE VDD PULSE GENERATOR LOAD INH RL CL A B C
Vout
Figure 5. V Across Switch
Figure 6. Propagation Delay Times, Control and Inhibit to Output
A, B, and C inputs used to turn ON or OFF the switch under test.
A B C Vout RL Vin VDD - VEE 2 VDD - VEE 2 Vin CL = 50 pF INH A B C ON
RL
VSS
INH
OFF Vout RL CL = 50 pF
Figure 7. Bandwidth and Off-Channel Feedthrough Attenuation
Figure 8. Channel Separation (Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST VDD A B C INH R1 COMMON RL CONTROL SECTION OF IC VEE OTHER CHANNEL(S) VEE VDD VEE VDD
Vout CL = 50 pF
Figure 9. Crosstalk, Control Input to Common O/I
NOTE: See also Figures 7 and 8 in the MC14016B data sheet.
Figure 10. Off Channel Leakage
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MC14051B, MC14052B, MC14053B
VDD KEITHLEY 160 DIGITAL MULTIMETER
10 k VDD VEE = VSS 1 k RANGE X-Y PLOTTER
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS
350 R ON , "ON" RESISTANCE (OHMS) R ON , "ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 350 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 TA = 125C 25C - 55C
TA = 125C 25C - 55C
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = - 7.5 V
700 RON , "ON" RESISTANCE (OHMS) R ON , "ON" RESISTANCE (OHMS) 600 500 400 300 TA = 125C 200 25C 100 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 - 55C 4.0 6.0 8.0 10 350 300 250 200 150
Figure 13. VDD = 5.0 V, VEE = - 5.0 V
TA = 25C
VDD = 2.5 V
5.0 V 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 7.5 V
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 14. VDD = 2.5 V, VEE = - 2.5 V
Figure 15. Comparison at 25C, VDD = - VEE
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MC14051B, MC14052B, MC14053B
APPLICATIONS INFORMATION Figure A illustrates use of the on-chip level converter detailed in Figures 2, 3, and 4. The 0-to-5 V Digital Control signal is used to directly control a 9 Vp-p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD - VSS = 5 V maximum swing above VSS ; VSS - VEE = 5 V maximum swing below VSS. The example shows a 4.5 V signal which allows a 1/2 volt margin at each
+5 V VDD VSS VEE + 4.5 V +5 V 9 Vp-p ANALOG SIGNAL SWITCH I/O
peak. If voltage transients above VDD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and V EE. Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10 V, VSS = + 5 V, and VEE - 3 V is acceptable. See the Table below.
-5 V
COMMON O/I MC14051B MC14052B MC14053B
9 Vp-p ANALOG SIGNAL
GND
EXTERNAL CMOS DIGITAL CIRCUITRY
- 4.5 V
0-TO-5 V DIGITAL CONTROL SIGNALS
INHIBIT, A, B, C
Figure A. Application Example
VDD DX ANALOG I/O DX COMMON O/I DX VDD DX
VEE
VEE
Figure B. External Germanium or Schottky Clipping Diodes
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POSSIBLE SUPPLY CONNECTIONS
VDD In Volts +8 +5 +5 +5 VSS In Volts 0 0 0 0 VEE In Volts -8 Control Inputs Logic High/Logic Low In Volts + 8/0 + 5/0 + 5/0 + 5/0 Maximum Analog Signal Range In Volts + 8 to - 8 = 16 Vp-p - 12 0 + 5 to - 12 = 17 Vp-p + 5 to 0 = 5 Vp-p -5 -5 + 5 to - 5 = 10 Vp-p + 10 +5 + 10/ + 5 + 10 to - 5 = 15 Vp-p
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MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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9
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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10
EEE CCC EEE CCC
M
9
-W-
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
16 9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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11
MC14051B, MC14052B, MC14053B
ORDERING & SHIPPING INFORMATION:
Device MC14051BCP MC14051BD MC14051BDR2 MC14051BDT MC14051BDTEL MC14051BDTR2 MC14051BF MC14051BFEL Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 TSSOP-16 SOEIAJ-16 SOEIAJ-16 Shipping 2000 Units per Box 48 Units per Rail 2500 Units / Tape & Reel 96 Units per Rail 2000 Units / Tape & Reel 2500 Units / Tape & Reel See Note 7. See Note 7.
ORDERING & SHIPPING INFORMATION:
MC14053BCP MC14053BD MC14053BDR2 MC14053BDT MC14053BDTEL MC14053BDTR2 MC14053BF MC14053BFEL PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 TSSOP-16 SOEIAJ-16 SOEIAJ-16 2000 Units per Box 48 Units per Rail 2500 Units / Tape & Reel 96 Units per Rail 2000 Units / Tape & Reel 2500 Units / Tape & Reel See Note 7. See Note 7.
7. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
MC14052BCP MC14052BD MC14052BDR2 MC14052BDT MC14052BDTR2 MC14052BF MC14052BFEL
PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 SOEIAJ-16 SOEIAJ-16
2000 Units per Box 48 Units per Rail 2500 Units / Tape & Reel 96 Units per Rail 2500 Units / Tape & Reel See Note 7. See Note 7.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
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12
MC14051B/D

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